Lithographic projection apparatus (tools) can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, the mask contains a circuit pattern corresponding to an individual layer of the IC, and this pattern can be imaged onto a target portion (e.g. comprising one or more dies) on a substrate (silicon wafer) that has been coated with a layer of radiation-sensitive material (resist). In general, a single wafer will contain a whole network of adjacent target portions that are successively irradiated via the projection system, one at a time. In one type of lithographic projection apparatus, each target portion is irradiated by exposing the entire mask pattern onto the target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus—commonly referred to as a step-and-scan apparatus—each target portion is irradiated by progressively scanning the mask pattern under the projection beam in a given reference direction (the “scanning” direction) while synchronously scanning the substrate table parallel or anti-parallel to this direction; since, in general, the projection system will have a magnification factor M (generally <1), the speed V at which the substrate table is scanned will be a factor M times that at which the mask table is scanned. More information with regard to lithographic apparatus as here described can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
In a manufacturing process using a lithographic projection apparatus, a mask pattern is imaged onto a substrate that is at least partially covered by a layer of radiation-sensitive material (resist). Prior to this imaging step, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a post-exposure bake (PEB), development, a hard bake and measurement/inspection of the imaged features. This array of procedures is used as a basis to pattern an individual layer of a device, e.g. an IC. Such a patterned layer may then undergo various processes such as etching, ion-implantation (doping), metallization, oxidation, chemo-mechanical polishing, etc., all intended to finish off an individual layer. If several layers are required, then the whole procedure, or a variant thereof, will have to be repeated for each new layer. Eventually, an array of devices will be present on the substrate (wafer). These devices are then separated from one another by a technique such as dicing or sawing. Thereafter, the individual devices can be mounted on a carrier, connected to pins, etc. Further information regarding such processes can be obtained, for example, from the book “Microchip Fabrication: A Practical Guide to Semiconductor Processing”, Third Edition, by Peter van Zant, McGraw Hill Publishing Co., 1997, ISBN 0-07-067250-4, incorporated herein by reference.
The lithographic tool may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic tools are described, for example, in U.S. Pat. No. 5,969,441 and WO 98/40791, incorporated herein by reference.
The photolithography masks referred to above comprise geometric patterns corresponding to the circuit components to be integrated onto a silicon wafer. The patterns used to create such masks are generated utilizing CAD (computer-aided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way.
Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the wafer (via the mask). Another goal is to use as much of the semiconductor wafer real estate as possible. As the size of an integrated circuit is reduced and its density increases, however, the CD (critical dimension) of its corresponding mask pattern approaches the resolution limit of the optical exposure tool. The resolution for an exposure tool is defined as the minimum feature that the exposure tool can repeatedly expose on the wafer. The resolution value of present exposure equipment often constrains the CD for many advanced IC circuit designs.
Patterning IC device features with size and pitch dimensions well below exposure wavelength on the resist-coated wafers with sufficient process latitude has become a significant manufacturing challenge today. With unforeseen economical and technical challenges for the next generation lithography, the semiconductor industry has become more interested in extending the existing exposure wavelength technology. According to the following Raleigh Criterion, if one is to use the same exposure wavelength, in order to shrink the design rule minimum feature pitch from one generation to the next, either a higher numerical aperture exposure tool or a lower k1 parameter must be utilized. In the last 20 years, the parameter k1 has been generally regarded as the lithography process capability. The lower k1, the more difficult the process becomes. The minimum pitch can be defined as:
            1      2        ⁢    Minimum    ⁢                  ⁢    Pitch    =            k      1        ⁡          (              Wavelength                  Numerical          ⁢                                          ⁢          Aperture                    )      While the industry has been pushing exposure tool suppliers to develop very high numerical aperture exposure tools (NA>0.90), it is also searching for methods to allow process capabilities to achieve lower k1 for manufacturing. It is clear that low k1 photolithography methods are now the mainstream for semiconductor manufacturing. Among the many low k1 techniques, the use of high NA and off-axis illumination (OAI) in combination with binary or phase-shifted masks (PSM) with optical proximity correction (OPC) are known. The scattering bar (SB) or assist feature OPC is particularly attractive and has been used in actual manufacturing since it is economical and can be effectively applied to all critical masking layers in both clear and dark field mask types.
As explained in detail, for example, in U.S. Pat. Nos. 5,242,770 and 5,447,810, SB OPC refers to sub-resolution assist features which are added to the original design features on the mask. The SBs operate to enhance the printing of main features, but the SBs themselves should not be printable. As such, SBs interact with main features within optical proximity range to enhance the printing of the main feature, while the SBs themselves are not printable. This is feasible in part by carefully adjusting the width of SB features to be below the printing resolution and also by taking the advantage of the non-linear response of photoresist. In order to achieve the greatest benefit from the deployment of SBs, the placement of the SB must be optimized. For line or trench structures, SB placement rules can be developed in a rather straightforward manner.
However, in order to meet the printing performance requirement for pitch features at sub-wavelength for any two-dimensional (2D) features such as contact or via holes, it is currently not possible to achieve satisfactory printing performance based on the existing rule-based methods. This is due to the fact that it is extremely difficult to apply a rule-based approach to achieve optimum placement of SBs for enhancing, for example, the printing of sub-wavelength pitch contact holes.
A model-based, automatic placement approach for applying SBs to a mask design has been investigated as a possible solution to the foregoing problem associated with utilizing a rule-based approach. For example, U.S. patent application Ser. No. 10/756,830 filed on Jan. 1, 2004, and Ser. No. 10/878,490 filed Jun. 29, 2004, both of which are assigned to the assignee of the instant application, and which are both incorporated herein by reference in their entirety, disclose a concept of placing SBs and non-printable phase features in the mask design utilizing interference maps (IM). While the concept has been demonstrated feasible for manufacturing purposes, it can still be a challenging process to apply the concepts into a manufacturing worthy implementation, especially when dealing with complex mask designs.
Accordingly, there remains a need for a method of applying SBs to a mask design based on interference maps generated from the target mask design which simplifies the application process and which further improves printing performance.